Synopsys Analog Layout Apprenticeship 2026 Bengaluru
Synopsys Off Campus Drive 2026 : Job Overview
Synopsys Off Campus Drive 2026 | Freshers | Analog Layout Apprentice | B.E / B.Tech (ECE / EEE / VLSI / EIE / EE or related) | 2026 / 2025 / 2024 Batch | Bengaluru, Karnataka (In-office). Visit our OffCampusDrive.co.in site for Off Campus Drive, Off Campus Placement, Internships, Pool Campus Drive, Joint Campus Drive, Walk-in Interview.
Job Role
Work as an Analog Layout Apprentice with Synopsys layout team in Bengaluru, supporting development of analog and mixed-signal CMOS layouts for next‑generation silicon chips.
Required Skills
Strong academic background in Electronics / Electrical / ECE / EEE / VLSI or closely related engineering branches. Basic knowledge of CMOS layout fundamentals, device structures and standard layout practices studied during coursework or projects. Understanding of design rules, parasitics and second‑order effects that impact analog and mixed‑signal layout quality. Willingness to learn industry EDA tools and follow Synopsys layout flows, checklists and documentation standards. Good analytical thinking with interest in solving layout-related challenges and debugging physical design issues with guidance. Familiarity with MS Office tools (Excel, Word, PowerPoint) for preparing technical reports, checklists and status updates. Clear communication skills to coordinate with senior layout engineers and global project teams on tasks and timelines. Ability to work full-time from the Bengaluru office for the complete 12‑month apprenticeship duration starting March/April 2026. Positive attitude, eagerness to pick up new concepts quickly and readiness to build a career in VLSI / analog layout domain.Job Responsibilities
Support layout engineers in building analog and mixed-signal CMOS layouts based on provided circuit schematics and guidelines. Interpret schematic diagrams, understand device connectivity and assist in planning floorplans for various analog blocks. Help create transistor-level layouts, matching structures and critical routing while adhering to design rules and constraints. Participate in physical verification (DRC/LVS and related checks) to ensure that layouts meet foundry and project requirements. Work with the team to identify, troubleshoot and fix layout issues observed during verification and design reviews. Follow established Synopsys layout methodologies, naming conventions, version control practices and documentation processes. Coordinate with global teams when needed to provide status updates and clarify layout-related queries for assigned blocks. Use office productivity tools for maintaining task trackers, preparing review slides and documenting learnings from the apprenticeship. Contribute to continuous improvement by sharing feedback on flows and actively participating in training sessions and knowledge-sharing meetings.| Field | Details |
|---|---|
| Company Name | Synopsys |
| Employment Type | Apprenticeship (12 Months) |
| Job Title | Analog Layout Apprentice |
| Job Category | Off Campus |
| Location | Bengaluru, Karnataka (In-office) |
| Education | B.E / B.Tech in ECE / EEE / VLSI / EIE / EE or related |
| Batch | 2025 / 2024 Batch |
| Experience | Freshers |
| Salary / CTC | Not Disclosed |
| Last Date | ASAP |
How To Apply Synopsys Off Campus Drive?
Interested and eligible candidates must complete the job Application form as soon as possible using the official link provided below.
Frequently Asked Questions
1. What is the Synopsys Analog Layout Apprenticeship 2026?
It is a 12‑month full-time apprenticeship program in Bengaluru where fresh engineering graduates work with Synopsys teams on analog and mixed-signal CMOS layout development.
2. Which batches are eligible for the Synopsys Off Campus Drive 2026?
The apprenticeship is targeted at freshers from the Class of 2024 and 2025 who meet the specified degree and branch requirements mentioned in the notification.
3. What qualifications are required for the Analog Layout Apprentice role?
Applicants should hold a B.E or B.Tech degree in Electronics, Electrical, ECE, EEE, VLSI, EIE or a closely related discipline from a recognized institute.
4. Is this apprenticeship work from home or in-office?
The job description clearly mentions an in‑office working model at the Bengaluru location, so candidates must be ready to work from the office throughout the program.
5. Can candidates pursuing M.Tech or other postgraduate programs apply?
As per the eligibility section, candidates should not be enrolled in M‑Tech or postgraduate diploma programs and should not be working full‑time elsewhere while joining the apprenticeship.
6. Is there any prior experience required to apply for this role?
This opportunity is designed for freshers; formal industry experience is not mandatory, but basic understanding of CMOS layout concepts and willingness to learn tools is expected.
7. Does Synopsys provide stipend for this Analog Layout Apprenticeship?
The external job post mentions that a competitive stipend is offered as per company norms, though the exact amount is not disclosed and should be checked on the official careers page.
8. What are the main skills I should focus on before the interview?
You should strengthen basics of electronics, CMOS layout principles, design rules, problem‑solving approach and be ready to discuss academic projects relevant to VLSI or layout work.
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